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24-bit quadrature counter features: ? programmable modes are: up/down, binary, bcd, 24 hour clock, divide-by-n, x1 or x2 or x4 quadrature and single-cycle. ? dc to 25mhz count frequency. ? 8-bit i/o bus for up communication and control. ? 24-bit comparator for pre-set count comparison. ? readable status register. ? input/output ttl and cmos compatible. ? 3v to 5.5v operation (v dd - v ss ). ? ls7166 (dip); ls7166-s (soic); ls7166-ts24 (24-pin tssop) - see figure 1 - general description: the ls7166 is a cmos, 24-bit counter that can be pro- grammed to operate in several different modes. the oper- ating mode is set up by writing control words into internal control registers (see figure 8). there are three 6-bit and one 2-bit control registers for setting up the circuit functional characteristics. in addition to the control registers, there is a 5-bit output status register (osr) that indicates the current counter status. the ic communicates with external circuits through an 8-bit three state i/o bus. control and data words are written into the ls7166 through the bus. in addition to the i/o bus, there are a number of discrete inputs and out- puts to facilitate instantaneous hardware based control func- tions and instantaneous status indication. register description: internal hardware registers are accessible through the i/o bus (d0 - d7) for read or write when cs = 0. the c/d in- put selects between the control registers (c/d = 1) and the data registers (c/d = 0) during a read or write operation. (see table 1) the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. august 2006 figure 1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 1 2 3 5 w a l t w h i t m a n r o a d , m e l v i l l e , n y 1 1 7 4 7 ( 6 3 1 ) 2 7 1 - 0 4 0 0 f a x ( 6 3 1 ) 2 7 1 - 0 4 0 5 ls7166 pin assignments - top view 7166-082906-1 20-pin dip and soic lctr/lltc abgt/rctr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lsi ls7166 d1 d2 d3 d4 d5 d6 d7 cy bw c/d rd v ss ( -v ) wr cs v dd ( +v ) a b d0 24-pin tssop 1 2 3 4 5 6 7 8 9 15 16 17 18 19 20 21 22 23 24 lsi ls7166 12 cs wr nc nc nc a lctr/lltc abgt/rctr b d0 d1 d2 v ss (-v) d3 d4 d5 d6 d7 nc v dd ( +v ) c/d rd bw cy 11 10 13 14 u l a3800
pr (preset register ). the pr is the input port for the cntr. the cntr is loaded with a 24 bit data via the pr. the data is first written into the pr in 3 write cycle sequence of byte 0 (pr0), byte 1 (pr1) and byte 2 (pr2). the address pointer for pr0/pr1/pr2 is automatically incremented with each write cycle. accessed by : write when c/d = 0, cs = 0. bit # 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 pr2 pr1 pr0 (byte 2) (byte 1) (byte 0) standard sequence for loading pr and reading cntr : 1 mcr ; reset pr address pointer write pr ; load byte 0 and into pr0 increment address write pr ; load byte 1 and into pr1 increment address write pr ; load byte 2 and into pr3 increment address 8 mcr ; transfer pr to cntr mcr (master control register) . performs register reset and load operations. writing a "non-zero?word to mcr does not require a follow-up write of an ?ll-zero?word to terminate a designated operation. accessed by : write when c/d = 1, cs = 0. bit # 7 6 5 4 3 2 1 0 0 0 1: reset pr/ol address pointer 1: transfer cntr to ol (24 bits) 1: reset cntr, bwt and cyt. set sign bit. (cntr = 0, bwt = 0, cyt = 0, sign = 1) 1: transfer pr to cntr (24 bits) 1: reset compt (compt = 0) 1: master reset. reset cntr, icr, occr, qr, bwt, cyt, ol compt, and pr/ol address pointer. set pr (pr = ffffff) and sign. 0: select mcr 0: note : control functions may be combined. icr (input control register) . initializes counter input operating modes. accessed by : write when c/d = 1, cs = 0. bit # 7 6 5 4 3 2 1 0 0 1 0: input a = up count input, input b = down count input 1: input a = count input, input b = count direction input (overridden in quadrature mode) where b = 0 selects up count mode and b = 1 selects down count mode. ( note : during counting operation b may switch only when a = 1.) 0: nop 1: increment cntr once (a/b = 1, if enabled) 0: nop 1: decrement cntr once (a/b = 1, if enabled) 0: disable inputs a/b 1: enable inputs a/b 0: initialize pin 4 as cntr reset input (pin 4 = rctr) 1: initialize pin 4 as enable/disable gate for a/b inputs (pin 4 = abgt) 0: initialize pin 3 as cntr load input (pin 3 = lctr) 1: initialize pin 3 as ol load input (pin 3 = lltc) 1: select icr 0: note : control functions may be combined. 7166-110103-2
osr (output status register) . indicates cntr status: accessed by : read when c/d = 1, cs = 0. bit # 7 6 5 4 3 2 1 0 u u u 0/1 0/1 0/1 0/1 0/1 bwt. borrow toggle flip-flop. toggles everytime cntr underflows generating a borrow. cyt. carry toggle flip-flop. toggles everytime cntr overflows generating a carry. compt. compare toggle flip-flop. toggles everytime cntr equals pr sign. sign bit. reset ( = 0) when cntr underflows set ( = 1) when cntr overflows up/down. count direction indicatior in quadrature mode. reset ( = 0) when counting down set ( = 1) when counting up (forced to 1 in non-quadrature mode) ol(output latch ). the ol is the output port for the cntr. the 24 bit cntr value at any instant can be accessed by performing a cntr to ol transfer and then reading the ol in 3 read cycle sequence of byte 0 (ol0), byte 1 (ol1) and byte 2 (ol2). the address pointer for ol0/ol1/ol2 is automatically incremented with each read cycle. accessed by : read when c/d = 0, cs = 0. bit # 7 0 7 0 7 0 ol2 ol1 ol0 (byte 2) (byte 1) (byte 0) standard sequence for loading and reading ol : 3 mcr ; reset ol address pointer and transfer cntr to ol read ol ; read byte 0 and increment address read ol ; read byte 1 and increment address read ol ; read byte 2 and increment address table 1 - register addressing modes d7 d6 c/d rd wr cs comment x x x x x 1 disable chip for read/write 0 0 1 1 0 write to master control register (mcr) 0 1 1 1 0 write to input control register (icr) 1 0 1 1 0 write to output/counter control register (occr) 1 1 1 1 0 write to quadrature register (qr) x x 0 1 0 write to preset register (pr) and increment register address counter. x x 0 1 0 read output latch (ol) and increment register address counter x x 1 1 0 read output status register (osr). x = don't care u = undefined 7166-110103-3
occr (output control register) initializes cntr and output operating modes. accessed by : write when c/d = 1, cs = 0. bit # 7 6 5 4 3 2 1 0 1 0 0 : binary count mode (overridden by d3 = 1). 1 : bcd count mode (overridden by d3 = 1) 0 : normal count mode 1 : non-recycle count mode. (cntr enabled with a load or reset cntr and disabled with generation of carry or borrow. in this mode no external cy or bw is generated. instead cyt or bwt should be used as cycle completion indicator.) 0 : normal count mode 1 : divide by n count mode (cntr is reloaded with pr data upon carry or borrow). 0 : binary or bcd count mode (see d0) 1 : 24 hour clock mode with byte 0 = sec, byte 1 = min and byte 2 = hr. (overrides bcd/binary modes) 0 pin 16 = cy, pin 17 = bw. (active low) 0 1 pin 16 = cyt, pin 17 = bwt 0 0 pin 16 = cy, pin 17 = bw. (active high) 1 1 pin 16 = comp, pin 17 = compt 1 0 select occr 1 qr (quadrature register) . selects quadrature count mode (see fig. 7) accessed by : write when c/d = 1, cs = 0. bit # 7 6 5 4 3 2 1 0 1 1 x x x x 0 disable quadrature mode 0 1 enable x1 quadrature mode 0 0 enable x2 quadrature mode 1 1 enable x4 quadrature mode 1 1 select qr 1 7166-110103-4 x = don? care
dc electrical characteristics . (all voltages referenced to v ss . t a = 0? to 85?c, v dd = 3v to 5.5v, fc = 0, unless otherwise specified) parameter symbol min. value max.value unit remarks supply voltage v dd 3.0 5.5 v - supply current i dd - 350 a outputs open input low voltage v il 0 0.8 v - input high voltage v ih 2.0 v dd v - output low voltage v ol - 0.4 v 4ma sink, v dd = 5v output high voltage v oh 2.5 - v 200a source, v dd = 5v input current - - 15 na leakage current output source current i src 200 - a v oh = 2.5v, v dd = 5v output sink current i sink 4 - ma v ol = 0.4v, v dd = 5v data bus off-state leakage current - - 15 na - absolute maximum ratings: parameter symbol values unit voltage at any input v in v ss - 0.3 to v dd + 0.3 v operating temperature t a -40 to +125 o c storage temperature t stg -65 to +150 o c supply voltage v dd - v ss +7.0 v 7166-082906-5 i/o description: (see register description for i/o prgramming.) data-bus (d0 - d7) (pin 8 - pin 15). the 8-line data bus is a three-state i/o bus for interfacing with the system bus. cs (chip select input) (pin 2). a logical "0" at this input enables the chip for read and write. rd (read input) (pin 19). a logical "0" at this input enables the osr and the ol to be read on the data bus. wr (write input) (pin 1). a logical "0" at this input enables the data bus to be written into the control and data registers. c/d (control/data input) (pin 18). a logical "1" at this input en- ables a control word to be written into one of the four control reg- isters or the osr to be read on the i/o bus. a logical "0" enables a data word to be written into the pr, or the ol to be read on the i/o bus. a (pin 6). input a is a programmable count input capable of functioning in three different modes, such as up count input, down count input and quadrature input. in non-quadrature mode, the counter advances on the rising edge of input a. b (pin 7). input b is also a programmable count input that can be programmed to function either as down count input, or count direction control gate for input a, or quadrature input. in non- quad- rature mode, and when programmed as the down count input, the counter advances on the rising edge of input b. when b is pro- grammed as the count direction control gate, b = 0 enables a as the up count input and b = 1 enables a as the down count input. when programmed as the direction input, b can switch state only when a is high. abgt/rctr (pin 4). this input can be programmed to function as either inputs a and b enable gate or as external counter reset input. a logical "0" is the active level on this input. in non- quadrature mode, if pin 4 is programmed as a and b enable gate input, it may switch state only when a is high (if a is clock and b is direction) or when both a and b are high (if a and b are clocks). in quadrature mode, if pin 4 is programmed as a and b enable gate, it may switch state only when either a or b switches. lctr/lltc (pin 3 ) this input can be programmed to function as the external load command input for either the cntr or the ol. when programmed as counter load input, the counter is loaded with the data contained in the pr. when programmed as the ol load input, the ol is loaded with data contained in the cntr. a logical "0" is the active level on this input. cy (pin 16) this output can be programmed to serve as one of the following: a. cy. complemented carry out (active "0"). b. cy. true carry out (active "1"). c. cyt. carry toggle flip-flop out. d. comp. comparator out (active "0") bw (pin 17) this output can be programmed to serve as one of the following: a. bw. complemented borrow out (active "0"). b. bw. true borrow out (active "1"). c. bwt. borrow toggle flip-flop out. d. compt. comparator toggle output. v dd (pin 5 ) supply voltage positive terminal. v ss (pin 20 ) supply voltage negative terminal.
transient characteristics (see timing diagrams in fig. 2 thru fig. 7, v dd = 3v to 5.5v, t a = 0? to 85?c, unless otherwise specified) parameter symbol min.value max.value unit clock a/b "low t cl 18 no limit ns clock a/b "high" t ch 22 no limit ns clock a/b frequency fc 0 25 mhz (see note 1) clock up/dn reversal t udd 100 - ns delay lctr positive edge to t lc 100 - ns the next a/b positive or negative edge delay clock a/b to t cbl - 65 ns cy/bw/comp "low" propagation delay clock a/b to t cbh - 85 ns cy/bw/comp "high" propagation delay lctr and lltc pulse t lcw 60 - ns width clock a/b to cyt, bwt t tfh - 100 ns and compt "high" propagation delay clock a/b to cyt, bwt t tfl - 100 ns and compt "low" progagation delay wr pulse width t wr 60 - ns rd to data out delay t r - 110 ns (c l =20pf) cs, rd terminate to t rt - 30 ns data-bus tri-state data-bus set-up t ds 30 - ns time for wr data-bus hold time for wr t dh 30 - ns cs set-up time for rd t srs 0 - ns cs hold time for rd t srh 0 - ns back to back rd delay t rr 60 - ns rd to wr delay - 60 - ns c/d set-up time for rd t crs 0 c/d hold time for rd t crh 30 c/d set-up time for wr t cws 30 - ns c/d hold time for wr t cwh 30 - ns cs set-up time for wr t sws 60 - ns cs hold time for wr t swh 0 - ns back to back wr delay tww 60 - ns wr to rd delay - 60 - ns quadrature mode: clock a/b validation delay t cqv - 160 ns (see note 1) a and b phase delay t ph 208 - ns clock a/b frequency f cq - 1.2 mhz cy, bw, comp pulse width t cbw 85 200 ns note 1: in quadrature mode a/b inputs are filtered and required to be stable for at least t cqv length to be valid. 7166-011705-6
figure 2 . load counter, up clock, down clock, compare out, carry, borrow note 1 : the counter in this example is assumed to be operating in the binary mode. note 2 : no comp output is generated here, although pr = cntr. comp output is disabled with a counter load command and enabled with the rising edge of the next clock, thus eliminating invalid comp outputs whenever the cntr is loaded from the pr. note 3 : when up clock is active, the dn clock should be held "high" and vice versa. cntr=fffffd (pr=cntr) cntr=fffffe cntr=ffffff cntr=000000 cntr=000000 cntr=fffffe cntr=0000001 cntr=fffffd (pr=cntr) cntr=ffffff note 2 up clk (a) dn clk (b) q0 (internal) q1 (internal) comp cy bw ltcr t lcw t cl t udd t ch t cl t ch q2-q23 (internal) t lc up clk or dn clk cy cyt bw bwt comp compt figure 3. clock to cy/bw output propagation delays t cbl t cbh t tfh t cbl t cbh t tfh t tfh t tfl t tfl t cbl t cbh t tfl sign (internal) 7166-110103-7
q1 (internal) q2-q23 (internal) dn clk lctr cntr ld (internal) bw q0 (internal) cntr=3 =2 =1 =0 =3 =2 =1 =0 =3 figure 5. divide by n mode note: example of divide by 4 in down count mode cntr disabled cntr enabled cntr disabled cntr load (lctr or mcr based) cy or bw figure 6 . cycle once mode up clk or dn clk 7166-110103-8 c/d wr c/d rd t crs t crh data bus t rd valid output t wr t cws t cwh data bus figure 4. read/write cycles valid data t ds t dh t sws t swh cs t rt cs t srs t srh t rr t ww
7166-110503-9 t ph t ph a b upclk (x1) (internal) dnclk (x1) (internal) upclk (x2) (internal) dnclk (x2) (internal) upclk (x4) (internal) dnclk (x4) (internal) forward reverse up/dn (osr bit 4) cy bw figure 7. quadrature mode internal clocks t cbw t cbw t cqv t cqv
3 4 7 pr/ol address input buffer and decode logic (data-bus) 8-15 i/o buffer d0 - d7 18 1 19 2 d0, d6,d7 d0 - d7 d0 - d7 d0 - d7 d0 -d7 5 20 (+5v) v dd (gnd) v ss internal data bus d0 -d4 qr occr icr mcr pr0 b0 - b7 pr1 b8 - b15 pr2 dn clock up clock d0 - d7 pr/ol address b16 - b23 cntr b0 - b23 n1=n2 n1 n2 status logic ol0 ol1 ol2 q0 -q23 control logic osr figure 8. ls7166 block diagram 6 (load ctr/load latch) lctr/lltc (ab gate/load latch) abgt/rctr (count input) b (count input) a (control /data input) c/d (write input) wr (read input) rd (chip select input) cs 16 17 cy (carry out) bw (borrow out) comparator 7166-110103-10
7166-110503-11 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ale 8051 80c31 74hc573 7166 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 1 19 18 2 12 q8 wr/ rd/ d0 d1 d2 d3 d4 d5 d6 d7 c/d cs/ wr/ rd/ 19 note: port_0 is open drain output. add pull-up resistors to all port_0 i/0 lines. figure 9. 80c31/8051 to ls7166 interface in external address mode d1 q1 c 0c 1 d2 d3 d4 d5 d6 d7 d8 2 3 4 5 6 7 8 9 11 8 9 10 11 12 13 14 15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7
p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 1 2 3 4 5 6 7 8 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 8051 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txo rxo 17 16 29 30 11 10 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 vcc 31 19 18 9 12 13 15 14 er/vp x1 x2 reset int0 int1 t0 t1 /7166c/d /7166cs /7166rd /7166wr 5 16 17 6 7 3 4 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 1 19 18 2 /7166wr /7166rd /7166c/d /7166cs wr rd c/d cs 8 9 10 11 12 13 14 15 d0 d1 d2 d3 d4 d5 d6 d7 r 8 lctr/lltc rbgt/rctr cy bw vss 20 v dd vcc figure 10. 8751 interface to ls7166 in i/o mode ur ls7166 7166-092304-12
7166-110103-13 16 17 3 4 6 7 gnd v dd cy bw lctr/lltc rbgt/rctr a count in b count in d0 d1 d2 d3 d4 d5 d6 d7 8 9 10 11 12 13 14 15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 a0 cs/ 2 wr/ 1 rd/ 19 address decode d q clk q cl pr 74hc74 2 5 6 9 12 15 16 19 q0 q1 q2 q3 q4 q5 q6 q7 20 ls7166 +5v +5v 5 6 4 2 1 3 1 4 5 6 74hc08 u5 a u6 b 74hc04 1 2 3 4 74hc04 74hc08 u6 a u5 b 74hc373 68hc11a1 27 26 28 25 24 42 43 44 45 46 47 31 32 33 34 35 36 37 38 16 15 14 13 12 11 10 9 5 4 3 2 1 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda modb u1 30 29 39 41 40 8 7 6 17 18 19 20 22 21 xtal extal reset irq xird pa0 pa1 pa2 pe0 pe1 pe2 pe3 yrh yrl pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 3 4 7 8 13 14 17 18 1 11 u3 oc g d0 d1 d2 d3 d4 d5 d6 d7 c/d cs wr rd figure 11. ls7166 to 68hc11 interface 18 2 e as rw
7166-110503-14 address decoder a0 ior/ iow/ a8 a7 a6 a5 a4 a3 a2 a1 aen d7 d6 d5 d4 d3 d2 d1 d0 8 9 10 11 12 13 14 15 d0 d1 d2 d3 d4 d5 d6 d7 cs wr rd c/d 1 19 18 2 ior/ d0 d1 d2 d3 d4 d5 d6 d7 isa bus figure 12. ls7166 interface example a0 iow/ ls7166
7166-062306-15 68000 68008 68010 7166 data bus a0 decode d ck wr rd d0 - d7 r/w lds/uds dtack clk ls373 ck address s74 cs d q d q ck s74 s d ck s74 +v +v clock r figure 13. 68000 interface to ls7166 as r c/d q s s q r

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